1. Field of the Invention
This invention relates to the field of testing data processing apparatus. More particularly, this invention relates to testing data processing hardware.
2. Description of the Prior Art
It is known to provide microprocessor based systems with debugging functions that allow the user to interrogate the state of the processor core. Such debugging systems allow the processor core to be isolated from other parts of the data processing apparatus and, by forcing the processor core to execute certain instructions, the internal state of the processor core may be made visible.
In systems such as the AMD29200 integrated circuit produced by Advanced Micro Devices, these debug instructions are not loaded into the processor core via the normal data/instruction bus. Rather, the debug instructions are serially loaded via a scan chain of the JTAG type and then scanned onto the instruction/data bus. The serial loading of the instructions into the scan chain takes place under control of a test clock signal coordinated with the external device that is providing the serial instructions. The instructions which are loaded in this way execute at a much slower speed than is usual since, for example, for a 32-bit instruction 32 test clock cycles are needed to load the instruction before a test clock signal may be issued to the core to cause it to execute the instruction.
An object of the invention is to address the abovementioned problem.
Viewed from one aspect the invention provides apparatus for processing data, said apparatus comprising:
(i) a processor core operable under control of program instructions;
(ii) means for supplying a system clock signal to said processor core;
(iii) means for supplying a test clock signal to said processor core; and
(iv) clock selecting means for selecting between said system clock signal driving operation of said processor core and said test clock signal driving operation of said processor core,
(v) wherein said clock selecting means selects said system clock signal during normal operation and said test clock signal during loading of program instructions during test operation, said clock selection means being responsive to one or more clock selecting bits within a program instruction to be executed during said test operation to select either said test clock signal or said system clock signal for driving said processor core to execute that program instruction.
Providing this clock selecting feature allows the processor core to execute the instructions once loaded in accordance with the true system clock signal which it would use during normal operation. In this way, a more realistic test of the processor core operation may be made.
Particularly preferred embodiments of the invention are ones comprising at least one auxiliary circuit coupled to said processor core and driven by said system clock signal, said clock selecting means selecting said system clock signal during test operation to execute program instructions that use said auxiliary circuit.
The invention provides the highly desirable ability to examine the state of auxiliary circuits coupled to the processor core as well as the processor core itself. Processor cores may be fully static enabling them to utilise the external test clock signal, but auxiliary circuits of the type that are used with processor cores do not necessarily have this capability (e.g. DRAM requires continual refreshing at the system clock rate). Generally speaking the coordination of the operation of the processor core with its associated auxiliary circuits is delicate and one is less able to deviate from the system clock, e.g. data transfers must be synchronized with both the core and the auxiliary circuit utilising the same clock signal.
The invention provides the capability to load the instructions using the test clock signal and yet switch to execute those instructions with the system clock signal. This increases the utility of the test analysis that may be performed in this manner.
As suggested above, the auxiliary circuits coupled to the processor core may take many forms. However, the invention is particularly suited to systems in which the auxiliary circuits include memory circuits and coprocessors. Such auxiliary circuits may be fabricated on the same integrated circuit as the processor core and so analyzing the interaction between these circuits and the processor core would be very difficult to achieve in other manners.
In preferred embodiments of the invention there is provided an instruction pipeline via which program instructions are fed to said processor core, said clock selecting means receiving said one or more clock selecting bits from that pipeline stage of said instruction pipeline holding a next instruction to be executed by said processor core.
High performance microprocessors include instruction pipelines to increase processing speed. An instruction pipeline can be advantageously utilised by the invention to effectively buffer the clock selecting bits together with their associated program instructions in a manner that assists a smooth change in clock signal when this is required.
It will be appreciated that each program instruction during test operation may be loaded from the debugging control system in different ways, e.g. in parallel via a dedicated bus. However, it is particularly advantageous to provide a system in which during test operation, each program instruction, including said one or more clock selecting bits, is serially loaded under control of said test clock prior to being applied to said processor core.
Serial loading of the program instructions during test operation reduces the pin count of the device so easing a design constraint.
In preferred serial loading embodiments it is advantageous to provide a test scan chain into which said program instructions are serially loaded during test operation.
A test scan chain can be used for other functions, such as signal capture and stimulus application during hardware test. Thus, the test scan chain can be made to perform more than one role and so provide greater functionality for the area of chip surface that it occupies.
It will be appreciated that during normal operation the clock selecting bits will be irrelevant since normal operation utilises the system clock signal. Accordingly, in preferred embodiments, during normal operation, each program instruction is loaded in parallel from a program memory, said one or more clock selecting bits being separately added to said program instructions read from said program memory.
Adding the clock selecting bits after loading the program instructions means that the memory storing the program instructions for use in normal operation need not store the clock selecting bits which are redundant since they have the same value for such normal operation program instructions. In this way, the storage capacity of the program memory is better utilised.
Viewed from another aspect the invention provides a method of processing data, said method comprising the steps of:
(i) operating a processor core under control of program instructions;
(ii) supplying a system clock signal to said processor core;
(iii) supplying a test clock signal to said processor core; and
(iv) selecting between said system clock signal driving operation of said processor core and said test clock signal driving operation of said processor core,
(v) wherein said system clock signal is selected during normal operation and said test clock signal is selected during loading of program instructions during test operation, one or more clock selecting bits within a program instruction to be executed during said test operation controlling selection of either said test clock signal or said system clock signal for driving said processor core to execute that program instruction.
The above, and other objects, features and advantages of this invention will be apparent from the following detailed description of illustrative embodiments which is to be read in connection with the accompanying drawings.